| 摘要 |
PROBLEM TO BE SOLVED: To make a high-speed cock extraction circuit small in size and low in cost. SOLUTION: The phase of a signal resulting from applying 1/m frequency division to a received non return to zero signal is compared with the phase of a signal resulting from applying 1/n frequency division to an extracted clock signal outputted from a voltage controlled oscillator 7 in order to relax an operating speed of a phase comparator 4. However, a different phase comparator circuit is used for phase comparison between a leading edge of the frequency- divided input signal and the extracted clock signal or between a trailing edge of the frequency-divided input signal and the extracted clock signal, which is selected by an edge pulse select circuit 3. Then the respective edge pulses are used, and phase comparison is conducted accordingly. Then the outputs of the phase comparators controls the voltage controlled oscillator 7 via a low-pass filter 6. Thus the objective clock extraction circuit is configured. |
