| 摘要 |
For each memory cell of a non-volatile memory, first and second semiconductor regions are provided in a substrate to serve as a source and a drain respectively and a channel region is formed therebetween. On different areas of the channel region are provided first and second floating gates, on which a control gate is formed. Third and fourth semiconductor regions of the same conductivity type as that of the substrate are respectively located below the first and second floating gates and respectively adjacent the drain and source regions. The impurity concentration of the third and fourth semiconductor regions is higher than that of the substrate. A high electric field is produced by the third semiconductor region when the first and second semiconductor regions are biased at a first potential difference for trapping hot electrons into the first floating gate, and a high electric field is produced by the fourth semiconductor region when the first and second semiconductor regions are biased at a second potential difference opposite in sense to the first potential difference for trapping hot electrons into the second floating gate.
|
