| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of further increasing the speed by reducing the area of sub-word driver which is a weak point of a hierarchical word line system, while keeping the merit of this system. SOLUTION: This device is a 64 Mbits or 256 Mbits DRAM using the constitution of the hierarchical word line, and a main low decoder area, main word driver area, column decoder area, peripheral circuit/bonding pad area, memory cell sub-array, sense amplifier area, sub-word driver area, crossing area, etc., are formed on a semiconductor chip. The sub-word driver consists of two parts, one PMOS transistor MP1 and one NMOS transistor MN1, and it is constituted so that the low level of the main word line MWB is made to negative voltage and the output level of the sub-word line SW becomes 0 V at the time of non- selection and high level (VPP) at the time of selection. |
