| 摘要 |
PROBLEM TO BE SOLVED: To provide a DRAM cell device having 1 transistor memory cell as a memory cell, which can be produced in an integrated density necessary for 1 gigabit generation. SOLUTION: A DRAM cell device comprises one vertical MOS transistor per memory cell, wherein first source/drain regions S/D1, respectively, belong to two adjacent transistors and are in contact with one bit line B1, second source/drain regions S/D2 are connected to a memory intersection point Sp, and a gate electrode G is provided with two sides which are in contact with a gate oxidation film I2. |
