Programmable delay element

摘要

The invention provides a programmable delay element and a programmable slew rate element to allow post-fabrication adjustment and programming of input delay and output slew rate to iteratively alter input delay and output slew rate without redesign and refabrication of the circuit. The invention provides programmable memory cells coupled to a capacitive load via a plurality of switches. The capacitive load is coupled to a signal path and comprises a plurality of capacitors. The programmable memory cells selectively turn on the switches coupled to the capacitive load. In one FPGA implementation, the programmable memory cells are implemented in IOBs and are loaded with appropriate data during a device configuration stage. Delay equalization can be achieved by programming the memory cells such that the delays seen by device I/O pins are equal between IOBs and pads. The invention also provides a slew rate control circuit for an inverter or a buffer to provide an optimal slew rate. The slew rate control circuit comprises a plurality of memory cells coupled to a current mirror via a plurality of switches. Appropriate data are programmed or loaded into the memory cells to selectively turn the switches coupled to a current source on or off. The current mirror is also coupled to the inverter or buffer to control its supply current. The slew rate of the inverter or buffer is controlled via the memory cell programming.