发明名称 |
Loop optimization compile processing method |
摘要 |
The entire space of a loop is analyzed for dependencies between target array elements so that dependency ID's are assigned to the target array elements. Optimization is carried out on the basis of the dependency ID's. Dependency ID's covering dependency for an arbitrary turn of the loop are reassigned to the target array elements that have been subjected to optimization, whereupon a further optimization is carried out. An examination for identifying overlappings is carried out on the basis of the dependency ID assigned to the target array elements so that instruction scheduling is carried out.
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申请公布号 |
US5842022(A) |
申请公布日期 |
1998.11.24 |
申请号 |
US19960722945 |
申请日期 |
1996.09.27 |
申请人 |
FUJITSU LIMITED |
发明人 |
NAKAHIRA, TADASHI;HARAGUCHI, MASATOSHI |
分类号 |
G06F9/45;(IPC1-7):G06F9/45 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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