| 摘要 |
PROBLEM TO BE SOLVED: To provide a delay circuit device that generates a clock signal with no phase difference from an external clock signal over a wide frequency range and a wide power supply voltage range with low current consumption. SOLUTION: The circuit device is provided with delay circuit arrays 101, 102 that obtain an output from an optional position of a signal transmission path, discrimination circuits 111b, 111c that respectively receive outputs at two positions among three divisions of the delay circuit array 101, and three control circuits 103a, 103b, 103c, and the signal transmission direction is opposite in the delay circuit arrays 101, 102, the output of the delay circuit array 101 and the input of the delay circuit array 102 are sequentially connected to a closer input of the delay circuit array 101 and to a closer output of the delay circuit array 102 via a control circuit. Then a 1st signal is given to the delay circuit array 101 and the discrimination circuit latches whether or not the 1st signal is delivered to the two outputs and a 2nd signal is given to the three control circuits or below in response to latch data of the discrimination circuit after the lapse of an optional time from the input of the 1st signal and the 1st signal of the delay circuit array 101 is given to the delay circuit array 102 and the 1st signal of the delay circuit array 101 is deleted. |
