| 摘要 |
PROBLEM TO BE SOLVED: To provide an integrated circuit provided with a phase control loop that supplies two signals where frequencies are in a relation of a multiple, signal transfer parts are completely in phase, a phase shift with respect to a clock signal is kept constant even when the signal frequency changes. SOLUTION: The phase control loop is provided with an oscillator 3 whose oscillated frequency is controlled, a frequency divider 4 and a phase comparator 1 that compares a reference signal (CKREF) with an output signal of the frequency divider to control the frequency of the oscillator. The integrated circuit has a phase shifter 5 that gives a signal (CKNO) whose frequency is a multiple of an input frequency and whose phase is in phase with that of the signal from the oscillator to an output terminal of the oscillator 3, a data input terminal (data) connecting to an output terminal of the frequency divider 4 and a clock interface (clk) connecting to the output terminal of the phase shifter and also has a resynchronization module 6 that is simply configured with a D flipflop that gives a signal (CKREFO) whose frequency is equal to the frequency of the input signal (CKREF) and which is synchronously with the output signal of the phase shifter. |
