发明名称 TESTING CIRCUIT FOR STORAGE DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a testing circuit for a storage device such as a RAM (random access memory) which has an error correcting function. SOLUTION: This testing circuit is equipped with a test bit decoder 105 which specifies data to be tested and the bit position of an error correction code from an address for the RAM, an error correction code generating means 104 which generates the error correction code from write data, a bit inverting circuit 106 which inverts the value at the bit position of the above-mentioned error correction code, an error correcting means 108 which detects and corrects error bits of output data of the RAM and the error correction code, and a data check circuit which confirms the error detection and correction, and conducts a test for a 1-bit error of the RAM.
申请公布号 JPH10312337(A) 申请公布日期 1998.11.24
申请号 JP19970121324 申请日期 1997.05.12
申请人 KOFU NIPPON DENKI KK 发明人 MURAMATSU MASAHITO
分类号 G06F12/16 主分类号 G06F12/16
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