| 摘要 |
PROBLEM TO BE SOLVED: To provide fast sense operation and an enlarged sence margin. SOLUTION: In this device, the bit line of the memory cell array section 11 and that of the sense amplifier section 14 are connected through P-type transfer gates 12, 13 and the bit line amplitude of the sense amplifier section 14 is made larger than that of the memory cell array section. In addition, the pre-charge voltage of the bit line of the sense amplifier section 14 is made different from that of the bit line of the memory cell array section are made different. Therefore fast sense operation and a magnified sense margin are realized and a reliable sense operation is secured even when the power source voltage is made low. |
