TAPERING SIDEWALLS OF VIA HOLES

摘要

A method of tapering side walls of via holes and a tapered via hole structure for an integrated circuit is provided. Via holes having steep sidewalls are provided in an insulating layer overlying a conductive layer on a substrate, with an underlying conductive layer exposed at a bottom of each via hole. A protective layer is provided over the conductive layer in each via hole, and over the sidewalls. The via holes are then tapered by argon sputter etching to remove the protective layer and part of the insulating layer from the sidewall and around the peripheral edge of each via hole, thereby smoothly tapering the sidewall and providing a via hole increasing continuously in diameter from the bottom to the upper peripheral edge of the via hole. Via holes of multiple depths are simultaneously and smoothly tapered to the bottom of the via holes Any sputtered debris remaining in the via holes after the sputter etch step is removed by reactive ion etching to clean the conductive layer exposed in each via hole and allow for formation of reliable electrical contacts.