METHOD OF FORMING A CHIP SCALE PACKAGE, AND A TOOL USED IN FORMING THE CHIP SCALE PACKAGE

摘要

A method of assembling a plurality of semiconductor chips is provided. A portion of a semiconductor wafer containing the plurality of chips is provided. Each of the plurality of chips has a contact pattern area including a pattern of contacts on a surface of the chip. A respective section of a dielectric interposer is assembled to each respective one of the plurality of chips individually, without detaching the plurality of chips from the portion of the semiconductor wafer. Each section of interposer has a plurality of bonding pads near an outer periphery of the section, so that each bonding pad lies near the contact pattern area of the corresponding one of the plurality of chips. Each bonding pad is wire bonded to a respective one of the contacts on the front surface of the corresponding one of the plurality of chips. The bonding step includes: (1) bonding one end of each wire to a respective bonding pad of the interposer using micro-resistant welding or ultrasonic bonding, and (2) bonding the other end of each wire to a respective contact of the chip using ultrasonic bonding. If a defective bond is detected, a wire may be removed and replaced by wire bonding. An encapsulant is applied to encapsulate the wires on each of the plurality of chips. The encapsulated chips are cut from the semiconductor wafer. Wires may be bonded at the corners of the chip, and need not be perpendicular to the sides of the chip.