| 摘要 |
<p>An A/D converter (6) digitizes input video signals by using a clock pulse (53) from a VCO (4) of a PLL circuit (1). The frequency of the pulse (53) is fixed. After a pre-processing circuit (7) changes the number of scanning lines, the digital video signals are written in a field memory (10). From the momory (10), the video signals are read out by using a second clock pulse (63) generated from a PLL circuit (11). The frequency dividing ratio of a frequency divider (15) of the PLL circuit (11) is changed by means of a control signal. When the frequency dividing ratio is changed, the frequency of the clock pulse (63) is changed and the number of samples in 1H-section of the video signals read out from the memory (10) is changed. Since the number of the pixels in an effective video section of the written video signals is fixed, the ratio of the range of the 1H-section to that of the effective video section can be changed and, accordingly, horizontal size adjustment can be performed by changing the number of samples in the 1H-section on the reading-out side.</p> |
