A multiprocessor system including dual port memories (DPMs) each used as a shared memory circuit for a host CPU circuit and one of sub CPU circuits. Each sub CPU writes an operation information thereof in a monitor information memory portion of an associated DPM after data write to a data portion of the DPM every data collection. The host CPU references the operation information in the monitor information memory portion and reads data from the DPM after a normal operation of the sub CPU is confirmed. When the sub CPU operates abnormally, the host CPU resets the sub CPU operating abnormally. A watch-dog timer monitors only operation of the host CPU. <IMAGE>
申请公布号
DE69227272(D1)
申请公布日期
1998.11.19
申请号
DE1992627272
申请日期
1992.04.15
申请人
NEC CORP., TOKIO/TOKYO, JP
发明人
SAITO, SHIGEAKI, C/O NEC CORPORATION, MINATO-KU, TOKYO, JP