发明名称 VOLTAGE REGULATING CIRCUIT FOR ELIMINATING LATCH-UP
摘要 The invention concerns a voltage regulating circuit (1) capable of detecting "latch-up" disturbing the voltage to be regulated, eliminating said phenomenon and restoring the voltage at a predetermined level. Said circuit comprises a bipolar transistor (2), a resistor (5) and means supplying substantially constant voltage (6). Said circuit (1) also comprises voltage detecting means (11) arranged to receive the regulated voltage (Vreg), and supply a control voltage to said transistor (2) capable of controlling its being switched between a conductive state and a locked state, such that the transistor (2) is in locked state when a "latch-up" occurs causing the regulated voltage to fall below a first voltage level, and such that the transistor (2) is in conductive state, when said regulated voltage is lower than a second voltage level, below which the "latch-up" phenomenon is eliminated.
申请公布号 CA2289935(A1) 申请公布日期 1998.11.19
申请号 CA19982289935 申请日期 1998.05.11
申请人 EM MICROELECTRONIC-MARIN S.A. 发明人 PONZETTA, ANTONIO MARTINO
分类号 H01L23/62;G05F1/00;G05F1/10;G05F1/56;G05F1/575;H02J1/00;H03K17/60;(IPC1-7):G05F1/00 主分类号 H01L23/62
代理机构 代理人
主权项
地址