Means for virtual deskewing of high/intermediate/low DUT data

摘要

A method and apparatus are provided for accomplishing virtual deskewing of device-under-test data received by a test system by skewing clock signals instead. In a preferred embodiment, the invention includes a receiver circuit (90) which is capable of operating in a window compare mode to capture a transition of a data signal from either a low data state to a high data state or a high data state to a low data state. The receiver circuit (90) receives a high-level comparator signal (HLC) and a low-level comparator signal (LLC), which when properly deskewed, together indicate what state the data signal is in. The state of the data signal may be one of a high data state wherein the data signal is above a high voltage threshold (VREFH), a low data state wherein the data signal is below a low voltage threshold (VREFL), or an intermediate state wherein the data signal is between the low voltage threshold (VREFL) and the high voltage threshold (VREFH). The receiver circuit (90) also receives a delayed high clock signal (CK_H) and a delayed low clock signal (CK_L) which differ in delay amount in an amount substantially equal to the data skew caused by different delays in respective data paths of the high-level comparator signal (HLC) and the low-level comparator signal (LLC). The delayed high clock signal (CK_H) is used to capture one or more window compare mode function outputs derived from the high-level comparator signal (HLC), and the delayed low clock signal (CK_L) is used to capture one or more window compare mode function outputs derived from said low-level comparator signal (LLC). The captured outputs of the window compare mode functions are decoded to assert one of a high data signal (HD) which indicates that the data signal is in the high data state, a low data signal (LD) which indicates that the data signal is in the low data state, or an intermediate signal (ID) which indicates that the data signal is in the intermediate state.