Arithmetic processing method and arithmetic processing device

摘要

An arithmetic processing method and arithmetic processing device each which can reduce the number of logical stages needed to obtain the final arithmetic result, thus executing an arithmetic process such as a floating-point multiplication at high speed to reduce the arithmetic process time. According to the arithmetic processing method and arithmetic processing device, the possibility that an arithmetic exception occurs in the arithmetic result obtained through an arithmetic process is judged in the middle of the arithmetic process of the dedicated arithmetic processing unit. Transmitting an arithmetic end signal to the instruction control unit is inhibited when it is judged that there is a possibility; the arithmetic process with the possibility is executed by means of another arithmetic unit different from the dedicated arithmetic unit. Thereafter the arithmetic end signal regarding the arithmetic process is transmitted to the instruction control unit. The arithmetic processing method and arithmetic processing device can be applied to the case where an arithmetic process such as a floating-point arithmetic operation is performed in a pipeline mode.