发明名称 Method of optimizing repeater placement in long lines of a complex integrated circuit
摘要 A method includes operating a general purpose computer system to minimize signal-propagation delay time of a long line of a simulated circuit. A design engineer empirically derives two rule bases, the first of which determines whether to divide the long line into two or more segments by inserting repeater amplifiers into a long line to minimize the propagation delay through the line. The second rule base relates optimum amplifier size for driving long lines to line length. These rule bases are stored in a main memory of the computer system. The computer system is configured to apply the first rule base to the long line to determine whether to divide the long line into two or more segments by inserting repeater amplifiers, and to apply the second rule base to optimize the size of each of the repeater amplifiers. The resulting long line, segmented by size-optimized repeater amplifiers, provides minimal signal-propagation delay.
申请公布号 US5838580(A) 申请公布日期 1998.11.17
申请号 US19960667908 申请日期 1996.06.20
申请人 SUN MICROSYSTEMS, INC. 发明人 SRIVATSA, CHAKRA R.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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