| 摘要 |
PROBLEM TO BE SOLVED: To obtain a radix-four FFT arithmetic circuit reduced at its circuit scale. SOLUTION: The FFT arithmetic circuit consists of a radix-four butterfly reference arithmetic circuit 1 having a 1st stage adder/subtracter group 11 constituted of four adder/subtracter groups and a 2nd stage adder/subtracter group 12 consisting of four adders and four subtracters for respectively inputting the combination of outputs from prescribed adders/subtracters out of eight outputs from the four adder/subtracter groups. Common necessary elements (a0 +a2 ), (a0 -a2 ), (a1 +a3 ), (a1 -a3 ), (b0 +b2 ), (b0 -b2 ), (b1 +b3 ), (b1 -b3 ) are previously calculated and output signals A,..., A, B,...B are found out by adding/ subtracting respective calculation results. Thus the adoption of the radix-four batteryfly reference arithmetic circuit 1 can sharply reduce its circuit scale as compared with a conventional circuit. |
