| 摘要 |
A line memory circuit is provided which simultaneously carries out line memory writing and line data comparison in order to improve high speed processing. The line memory circuit of the present invention has an information bit (line match/mismatch bit) encoded at the head of each line in the line memory circuit used in an encoding circuit, wherein encoding of a picture element data of the line is avoided when a matching result is obtained. In the line memory circuit, input picture element data are stored into a line memory, and the input data are sequentially compared with picture element data on the preceding line stored in the line memory. Picture element data on the preceding line are sequentially encoded during the next line. The line memory circuit completes encoding of input picture element data during a subsequent line where picture element data are inputted, which enables high speed encoding of the input picture element data.
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