Isolated vertical PNP transistor without required buried layer

摘要

A vertical PNP transistor and method for making it provide a transistor in a surface layer (12), which may be an epitaxial layer, of P- type conductivity at a surface of a substrate (11) of P+ type conductivity. An isolation region (14) of N- type conductivity in the P- surface layer (12) contains a collector region (25) of P- type conductivity. A base region (30) of N type conductivity is contained in the collector region (25), and an emitter region (40) of P+ type conductivity is contained in the base region (30). The base region (30) may be provided with a higher N type impurity concentration than a P type impurity concentration of the collector region (25). At least the collector region (25) and the base region (30) may be self aligned. The collector region (25) may be of thickness of about 2.2 mu m, the base region (30) of thickness of about 0.1 mu m, and the emitter region (40) of thickness of about 0.4 mu m. Although the transistor is vertically constructed, base and collector contacts (60 and 42-43) may be provided at a surface of the surface layer (12) opposite the substrate (11). A contact (62) may also be provided for the isolation layer (14) at the surface.