Simulation apparatus

摘要

The present invention is a simulation apparatus which can shorten the transmission and reception time of events, and unify simulation models to make it possible to use the same language expression as that for an ordinary model to express a real chip. The simulation apparatus comprises a real chip simulation section for carrying out simulation for a portion having an unknown internal logic by using a real chip, a logic simulation hardware section for carrying out simulation for a portion whose internal logic is described, and a high speed dedicated network for transferring event data between the real chip simulation section and the logic simulation hardware section. The simulation apparatus can be applied to hardware accelerators used in logic timing simulation in the field of CAE.