发明名称 Method of increasing package reliability using package lids with plane CTE gradients
摘要 A lid for a chip/package system includes a body sized to fit over an integrated circuit chip and being connectable to a package. The body has at least two regions exhibiting different coefficients of thermal expansion, with one CTE matching that of the chip and the other matching that of the package.
申请公布号 US5838063(A) 申请公布日期 1998.11.17
申请号 US19960744843 申请日期 1996.11.08
申请人 W. L. GORE & ASSOCIATES 发明人 SYLVESTER, MARK F.
分类号 H01L23/10;H01L23/373;(IPC1-7):H01L23/12;H01L23/06;H01L23/02 主分类号 H01L23/10
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