发明名称 NMOS charge-sharing prevention device for dynamic logic circuits
摘要 A logic block comprised of several transistors is provided. The logic block has several inputs and an output for communicating the result of its logic operation. A precharge device having a clock input is connected to the output of the logic block. The precharge device periodically allows the output of the logic block to become valid. This is accomplished by holding the output of the logic block at a fixed voltage level when the clock input is at a first voltage level, and when the clock input changes to a second voltage level, the precharge device allows the result of the logic function performed by the logic block to appear at the output of the logic block. Also, a charge redistribution prevention device is connected to at least one of the transistors included in the logic block. The charge redistribution prevention device prevents charge redistribution by applying a voltage to at least one of the transistors in the logic block. Applying a voltage in this manner equalizes the difference in voltage between internal nodes of the logic block and the output of the logic block, thereby preventing charge from redistributed.
申请公布号 US5838169(A) 申请公布日期 1998.11.17
申请号 US19960713881 申请日期 1996.09.17
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATOIN 发明人 SCHORN, ERIC BERNARD
分类号 H03K19/096;(IPC1-7):H03K19/096;H03K19/084 主分类号 H03K19/096
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