| 摘要 |
Isolated Partial Scan (IPS) circuits and methods provide a partial scan technique in which no blocking or isolation circuitry is required and which requires little extra circuitry, reduces the amount of added circuitry and eliminates the need for circuit design restrictions that are common to conventional design for testability (DFT) methods. IPS ensures by construction that the state of non-scan sequential devices is not changed during the scan operations of scan sequential devices without the need to add disabling logic to protect or isolate the non-scan devices from the scan devices. A partial scan test circuit has sequential scan elements for directly replacing sequential logic elements within a circuit. Each scan element performs the same function of the replaced sequential element and includes a data input, a data output, a scan input, a scan output, and control signals for controlling the operation of the scan element, including normal, scan in and scan out operations. The data output of each scan element does not change state during scan in or scan out operations. IPS offers the advantages of: (1) little or no propagation delay penalty, so performance is preserved, (2) smaller circuitry for testability, since only a subset of the flip flops need be scanned, so less area penalty is incurred, and (3) no extra design rules are required so the designer is free to design in accordance with meeting design objectives.
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