| 摘要 |
A phase detector arrangement for use in a phase locked loop circuit recovers clock and data pulses from a data stream comprising Return to Zero (RZ) signals including digital data. The arrangement includes a comparator, a phase detector, a loop filter, and a voltage controlled oscillator. The phase detector includes a phase position indicator which is activated by each incoming data pulse in the output line of the comparator. A method for recovering clock and data pulses includes the steps of monitoring the data pulses in each output line of the comparator and controlling the voltage controlled oscillator in relation to both edges of each data pulse, for clocking data synchronously with the pulse. |
