发明名称 DELAY CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To suppress the effects of condition fluctuations of a device and to provide constant delay by providing a fluctuation width adjusting part constituted of MOS transistors and resistances. SOLUTION: A delay addition part is constituted of a P-channel MOS transistor MP1, a resistor R1 and a capacitor C1. The fluctuation width adjusting part is constituted of the P-channel MOS transistors MP2 and MP3, N-channel MOS transistors MN1 and MN3 and the resistors R2 and R3. An output stage inverter part is constituted of a P-channel MOS transistor MP4 and an N- channel MOS transistor MN2. When the resistance values of the resistors R2 and R3 becomes large by a process change in the manufacture of a semiconductor, voltage between the gates and the sources of the transistors MP3 and MN3 becomes high. Then, the switching speed of the output stage inverter part becomes fast, and the fluctuation of delay time is suppressed.</p>
申请公布号 JPH10303711(A) 申请公布日期 1998.11.13
申请号 JP19970107094 申请日期 1997.04.24
申请人 NEC CORP 发明人 KIKUCHI TSUNEO
分类号 H03K5/13;(IPC1-7):H03K5/13 主分类号 H03K5/13
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