| 摘要 |
PROBLEM TO BE SOLVED: To provide an information processor in a pipe line processing system in which a processing speed can be increased without depending on the responding speed of a memory which stores a program. SOLUTION: In a CPU in a pipe line processing system, the basic bit length of an instruction set is set to be half of the bus width of the data line of an ROM, and the executing time T of an IF stage for reading an instruction from the ROM is set to be two times as long as that of the other stages (ID, EX, MA, and WB). Then, the CPU simultaneously reads two instructions from the ROM in one time of IF stage, and decodes and executes each instruction in an instruction processing cycle and the next instruction processing cycle having the IF stage, and executes the IF stage in each of the two instruction processing cycles and in a period in which two ID stages for decoding the instruction are present. The time T of the IF stage can be sufficiently ensured, and the time of the other stages can be shortened, and the processing speed of the instruction can be increased by this CPU. |
