发明名称 METHOD FOR SIMULATING ELECTRIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a means for inexpensively evaluating the electric characteristics of an electric circuit packaged on multi-layer substrate structure by using highly accurate and efficient simulation. SOLUTION: When an inductor component Lfeed 4 is added to an electric equavalent circuit(EEC) model 3 for a parallel plate built in a multi-layer substrate and an EEC model 2 for a through hole with respect to an EEC model for the multi-layer substrate having the metallic parallel plate and the metallic through hole, feeding point inductance generated due to the connection of the parallel plate to the through hole is modeled to efficiently improve the accuracy of the multi-layer substrate EEC model. An error in the resonance frequency of the electric circuit model is set up and the minimum scale and effective frequency range of the electric circuit model are determined, so that the calculation efficiency of simultation based on the multi-layer substrate EEC model can be improved.
申请公布号 JPH10301976(A) 申请公布日期 1998.11.13
申请号 JP19970112464 申请日期 1997.04.30
申请人 HITACHI LTD 发明人 AOYAGI PAUL;YAMAMURA HIDEO
分类号 G06F17/50;G06F17/00;G06F19/00 主分类号 G06F17/50
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