| 摘要 |
PROBLEM TO BE SOLVED: To provide a complex coefficient multiplier and a complex coefficient filter capable of reducing the scale of a circuit without reducing a processing speed by reducing the number of multipliers. SOLUTION: The multiplier multiplies a complex input signal (x+jy) by a complex coefficient (a+jb). In this case, a multiplier 2 multiplies (x) by (a+b) and a multiplier 4 multiplies (y) by (a-b). On the other hand, an adder 1 adds (x) to (y) and a multiplier 3 multiplies (x+y) by (b). An adder 5 calculates a difference between outputs from the multipliers 2, 3 and outputs the real part value pR of a complex output signal. An adder 6 calculates the sum of outputs from the multipliers 2, 3 and outputs the imaginary part value pI of the complex output signal. |
