| 摘要 |
<p>PROBLEM TO BE SOLVED: To drastically reduce clock skew, reducing delay time of a clock signal. SOLUTION: In a clock signal transmission circuit 1 which distributes a clock signal to a prescribed circuit, the threshold of an inverter Iv1000 is made large, the threshold of an inverter Iv100 on its preceding stage is made small, the threshold of an inverter Iv10 on its preceding stage is made large and the fall waveform of an inputted signal is propagated early, and skew is reduced by synchronizing with a clock signal whose delay time is short.</p> |
