发明名称 VIDEO SIGNAL CODER
摘要 PROBLEM TO BE SOLVED: To reduce the scale of an entire circuit of a coder. SOLUTION: An input video signal is fed to a selection circuit 109 via a delay element 111. A 1st predicted candidate signal 1 (2nd predicted candidate signal 2) is delayed by a delay element 112(113) separately and given via a differential operational arithmetic circuit 103(104) together with a delayed output video signal from the delay element 111 to a selection circuit 109, where any signal is selected based on an output of a comparator 108 and the selected signal is outputted as an optimum predicted error signal. Delayed output signals from the delay elements 112, 113 are fed to a selection circuit 110, where wither signal is selected based on an output of the comparator 108 and the selected signal is outputted as an optimum predicted signal. That is, the delay elements 111-113 are used to generate input signals for the selection circuits 109, 110 respectively.
申请公布号 JPH10304378(A) 申请公布日期 1998.11.13
申请号 JP19970112115 申请日期 1997.04.30
申请人 NEC CORP 发明人 YOSHIKAWA WATARU
分类号 H04N19/50;G06T9/00;H03M7/30;H03M7/36;H04N19/11;H04N19/136;H04N19/137;H04N19/196;H04N19/423;H04N19/426;H04N19/503 主分类号 H04N19/50
代理机构 代理人
主权项
地址