发明名称 Clock signal synchronising circuit
摘要 The circuit has a first phase comparator (33) comparing an external clock signal with preset tinme delay with a feed back clock signal to determine their relative phase displacement. A second phase comparator (34) compares the external clock signal with a feed back clock signal with preset time delay to determine their relative phase displacement. A charge pump (35) changes a level of charge depending on the phase deviation signals from the comparators. Depending on the level of charge provided by the charge pump a compensator (31) compensates the phase of the external clock signal. When the external and feedback signals are in syncdhronism a control circuit (32) switches the whole system into a low power mode.
申请公布号 DE19751269(A1) 申请公布日期 1998.11.12
申请号 DE19971051269 申请日期 1997.11.19
申请人 LG SEMICON CO., LTD., CHEONGJU, KR 发明人 WANG, SUNG HO, SEOUL, KR;JUN, YOUNG-HYUN, SEOUL, KR
分类号 G06F1/12;H03K19/00;H03L7/08;H03L7/081;H03L7/087;H04L25/40;(IPC1-7):H03L7/085;H03K5/26 主分类号 G06F1/12
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