Digital oscillator for desynchronizer in communications system

摘要

The digital oscillator generates a target clock (ZT) by variably dividing a working clock (AT) with first and second factors. An oscillator (Q) generates the working clock whose positive and negative edges trigger first and second divider circuits (TS1,TS2) which alternately receive a control word (SW) contg. at least one bit via a controlled switch (S1). A second switch (S2) alternately switches the divider circuits to a single output for the target clock. Each divider circuit contains a logic module for detecting an storing the occurrence of each positive or negative control word edge. The logic module causes a controlled changeover of the second switch in response to detecting a control word edge so that the working clock is divided by a second factor whilst maintaining the low or high level duration constant.