| 摘要 |
<p>Disclosed is a programmable memory test interface (206). The test interface includes logic circuitry configured to be integrated to a memory device. The memory device has a plurality of receiving connections that are configured to be coupled to a plurality of internal connections that couple to the logic circuit. The interface further includes a plurality of programmable input pins and output pins leading to and from the logic circuit, and the programmable input pins and output pins are configured to receive control signals from a test controller for operating the memory device in either a test mode or a mission mode. The programmable input pins and output pins are selectively interconnected to transform the logic circuitry into at least one type of memory testing methodology interface.</p> |
