发明名称
摘要 PURPOSE: To correct burst errors generated on a transmission line concerning the data transmitter for converting parallel digital signals to serial signals and transmitting them. CONSTITUTION: Two encoder circuits 1 on the transmission side perform (40, 32) SEC encoding to the parallel signals of eight-byte width while defining four bits as one byte and output the parallel signals of ten-byte width. An interleave circuit 12 distributes the respective bytes of these parallel signals into four pieces of parallel signals having ten-bit width. First and second parallel/serial(P/S) converting circuits 2 and 3 respectively perform the P/S conversion of 10:1 and 8:1. On the reception side, first and second S/P converting circuits 7 and 8 respectively perform the S/P conversion of 1:8 and 1:10. A deinterleave circuit 12 prepares the parallel signals of ten-byte width while defining four bits, which are collected from four of eight parallel signals having ten-bit width one by one as one byte. Two decoder circuits 9 correct the byte errors of these parallel signals and output the parallel signals of eight-byte width.
申请公布号 JP2822922(B2) 申请公布日期 1998.11.11
申请号 JP19950107920 申请日期 1995.04.08
申请人 发明人
分类号 H03M9/00;H03M13/27;H04J3/04;H04L1/00;(IPC1-7):H04L1/00;H03M13/22 主分类号 H03M9/00
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