发明名称 Dual-level metalization method for integrated circuit ferroelectric devices
摘要 <p>A dual-level metalization method for ferroelectric integrated circuits includes the steps forming a planarized oxide layer over a partially formed integrated circuit ferroelectric device, forming a cap layer over the planarized oxide layer, forming vias into the planarized oxide layer and cap layer to provide access to the desired first-level metal contacts, and metalizing the selected first-level metal contacts with second-level metal. The cap layer can be doped or undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, or manganates such as doped and undoped PZT (lead zirconate titanate), BST (barium strontium titanate), or SBT (strontium bismuth tantalate). <IMAGE></p>
申请公布号 EP0877422(A1) 申请公布日期 1998.11.11
申请号 EP19980302764 申请日期 1998.04.08
申请人 RAMTRON INTERNATIONAL CORPORATION;FUJITSU LIMITED 发明人 ARGOS, GEORGE;YAMAZAKI, TATSUYA
分类号 H01L21/28;H01L21/02;H01L21/31;H01L21/768;H01L21/8242;H01L21/8246;H01L21/8247;H01L23/00;H01L23/532;H01L27/10;H01L27/105;H01L27/108;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824;H01L21/320 主分类号 H01L21/28
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