| 摘要 |
<p>A circuit verification process is disclosed for verifying whether the circuit of a semiconductor device meets specifications for logical operations and also predetermining operation timing requirements, at the time of designing the semiconductor device. An address data macroblock having functions that are expected to be changed more often and a peripheral functional macroblock having general functions are prepared separately from each other. Only, the peripheral functional macroblock is registered in a library. When addresses of address decoders of the address data macroblock are changed, only the address data macroblock are redesigned, and the peripheral functional macroblock is used without being verified. <IMAGE></p> |
