Method for controlling data output buffer for use in operation at high frequency of synchronous memory

摘要

Methods and apparatus for controlling output buffer circuitry in a synchronous semiconductor memory device. An internal clock signal is generated and logic provided to provide a control signal that enables that output buffer circuitry for a read operation. An internal clock signal is generated synchronized to the external or system clock signal. An intermediate control signal is triggered by the internal clock signal at a selected number of cycles less than the memory latency period after a read command, and then the control signal for enabling the output buffer is asserted on a subsequent cycle of the internal clock signal, thereby ensuring at least a predetermined minimum time for the output buffer control signal to propagate through the memory device before data is transferred out of the device.