| 摘要 |
A circuit arrangement for deriving horizontal frequency and vertical frequency pulses from a synchronizing signal, in which all clocked components are provided with the same clock during the digital processing of the synchronizing signal. Too derive the horizontal (H) pulse signal, a logic circuit 2 is provided which combines the sync signal with a masking pulse signal derived from the clocked sync signal. To derive the vertical (V) pulse signal in the clock raster, a counting flip-flop 14 is driven by the clocked sync signal after combination with the vertical pulse signal via an interference pulse signal suppression circuit 10. To derive the 2V pulse signal, a logic circuit 17 is provided which combines the V pulse signal with a pulse signal derived from the clocked sync signal.
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