发明名称 |
Address space architecture for multiple bus computer systems |
摘要 |
An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.
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申请公布号 |
US5835738(A) |
申请公布日期 |
1998.11.10 |
申请号 |
US19960668530 |
申请日期 |
1996.06.24 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BLACKLEDGE, JR., JOHN WILEY;BOURY, BECHARA;FREY, BRADLY GEORGE;REID, JAMES D.;VALLI, RONALD |
分类号 |
G06F13/36;G06F13/40;H04L12/46;H04L29/12;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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