发明名称 Floating isolation gate from DRAM sensing
摘要 A method of operating a sense amplifier comprises floating an isolation gate line signal when a memory cell is being accessed. In one embodiment, the isolation gate is first turned on by biasing the gate line of the isolation gate. Then, the input of a sense amplifier is coupled to a desired memory cell and about the same time, the isolation gate is floated. The isolation gate is at least partially turned off by a reduction in the voltage level of the ISO gateline through capacitance based decay. This at least partially isolates other memory cells and/or circuitry accessed through a set of digit lines, allowing the sense amplifier to more easily sense the state of the desired memory cell. The isolation gate is floated by coupling the gate line of the isolation gate to a high impedance. The sense amplifier may be an N-sense amplifier. The isolation gate is floated prior to sense amplifier being activated. The voltage level of the ISO signal is reduced by parasitic coupling to other circuitry associated with the sense amplifier. Since the ISO gate is floated prior to the sense amplifier being activated, there is less sensitivity to timing inaccuracies. In addition, a resulting larger differential voltage on the digit lines is more easily and quickly sensed by the sense amplifier.
申请公布号 US5835433(A) 申请公布日期 1998.11.10
申请号 US19970871523 申请日期 1997.06.09
申请人 MICRON TECHNOLOGY, INC. 发明人 CASPER, STEPHEN L.
分类号 G11C7/06;G11C11/4091;(IPC1-7):G11C7/00 主分类号 G11C7/06
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