RULE INFERENCE AND LOCALIZATION DURING SYNTHESIS OF LOGIC CIRCUIT DESIGNS

摘要

A logic method for accessing rules in a logic circuit synthesis system. Rules are associated with model instances representing circuit components and contained in a data base. Application of the rules results in the replacement of one or more of the model instances with other model instances or in alteration of values associated with the model instances or in the alteration of parameter values in the data base. Model instances are designated as VISIBLE or INVISIBLE. INVISIBLE model instances are ignored during logic circuit synthesis. That is, the rules associated with INVISIBLE model instances are not tested. VISIBLE model instances may be NEW or INACTIVE. All VISIBLE model instances are initially NEW. If no rule associated with a model instance is TRUE, the model instance becomes INACTIVE. If at least one rule associated with a model instance is TRUE, one or more model instances are replaced and all inserted model instances and model instances directly connected to the inserted model instances become NEW. The number of model instances a rule will replace is called a SIZEWIN value of the rule. During synthesis, each VISIBLE, NEW model instance is paired with its associated rule having the greatest SIZEWIN value. The instance-rule pairs are grouped by SIZEWIN value and the rules of the groups having the greatest SIZEWIN value are tested first. The rules of the group having the smallest SIZEWIN value are tested last. If a model instance has been replaced by a previously executed rule, it is designated as DELETED and its associated, paired rule will evaluate to FALSE.