| 摘要 |
PCT No. PCT/DE95/01556 Sec. 371 Date Aug. 22, 1997 Sec. 102(e) Date Aug. 22, 1997 PCT Filed Nov. 10, 1995 PCT Pub. No. WO96/15502 PCT Pub. Date May 23, 1996In acquisition devices for analog measured values (Ue1 . . . Uen), there is frequently the problem that the digital processor (P) of said devices has a restricted binary word length (WP), as compared with the word length (WP) of the measured values in digitized form (AMD(Uen)). To permit unmodified rapid acquisition and digital conditioning of the measured values (AMD(Uen)), binary factors (NF, KF, VF) are preferably provided separately for each measured value (AMD(Uen)), said factors (NF, KF, VF) being combined (Equation 3) to form an element (K) which is processed by the processor (P) at an update rate which is lower in comparison with a sampling rate which is used to update the measured values (AMD(Uen)). As a result, the processing speed of the processor can be increased. It is also advantageous to provide a binary displacement factor (VF), by means of which the element (K) is expanded in a counter and the product of the element (K) and the respective digitized measured value (AMD(Uen)) is expanded in a denominator. The binary displacement factor (VF) is selected in such a way that the digital combination of the product with the displacement factor (VF) in the denominator corresponds to a loading operation of higher-order bits of the product by the processor (P).
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