| 摘要 |
An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of processing elements (PE) constituting a parallel computer system. An adder provided within the global address generating unit sequentially adds an increment of an address, d-Adr-exl, and d-Adr-in to an address Adr-exl and Adr-in, respectively. A subtracter outputs a quotient obtained by dividing d-Adr-exl by band width bexl as a logical PE number. Additionally, a remainder obtained as an output from a subtracter is added to Adr-in, thereby enabling a logical in-PE address to be obtained. The logical PE number and the logical in-PE address thus obtained are converted to a real PE number and a real in-PE address. Generating a global address by hardware reduces overhead incurred by parallel operation of array data.
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