发明名称 |
Methods and systems for improving memory component size and access speed including splitting bit lines and alternate pre-charge/access cycles |
摘要 |
A memory system having split logical bit lines and interleaved pre-charge/access cycles is provided. A bit line access circuit supports multiple conductors per logical bit line and pre-charges the conductors before access cycles thereto. The access cycles for one logical bit line are performed simultaneous with the pre-charge cycles for another logical bit line by the access circuit. Virtual reading is provided for eliminated memory cells. The memory system can be used in a programmable gate array having memory cells distributed throughout for programming respective programmable resources.
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申请公布号 |
US5836007(A) |
申请公布日期 |
1998.11.10 |
申请号 |
US19950528177 |
申请日期 |
1995.09.14 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CLINTON, KIM P. N.;KEYSER III, FRANK RAY;LARSEN, WENDELL RAY |
分类号 |
G11C11/41;G11C7/10;G11C7/12;G11C7/18;H01L27/112;H03K19/177;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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