| 摘要 |
The invention provides a high speed variable rate output pulse generating circuit for a semiconductor testing device. The circuit includes a shift register formed of 2n number of flip-flops which counts the lower bits of lower counter data selected by a selector, a ripple down counter formed of m number of flip-flops counts the upper bits of upper counter data selected by a NOR gate. A counting end judgment circuit for judging an end of counting the ripple down counter and the shift register produces a counting end signal. A first flip-flop latches the counting end signal to supply a counter load signal to the selector and the NOR gate to load subsequent data, and a second flip-flop generates a first output clock pulse.
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