发明名称 PLL frequency synthesizer using frequency dividers reset by initial phase difference
摘要 In a frequency synthesizer, a first, constant frequency divider is connected to a reference frequency oscillator, and a second, variable frequency divider is connected to a voltage-controlled oscillator. A phase difference is detected by a phase detector between the frequency dividers and a first output pulse or a second output pulse is produced when the second frequency divider is leading or lagging the first frequency divider. A charge pump integrates the first and second output pulses to supply a phase difference signal to a lowpass filter which drives rates the voltage-controlled oscillator. An initial phase difference which occurs between the frequency dividers immediately after they are energized is detected and one of the frequency dividers is reset with the detected phase difference to align their phase. As long as the initial phase difference is detected, the passages of the first and second output pulses to the charge pump are blocked.
申请公布号 AU6376198(A) 申请公布日期 1998.11.05
申请号 AU19980063761 申请日期 1998.05.01
申请人 NEC CORPORATION 发明人 JUN JOKURA
分类号 H03L7/18;H03L7/089;H03L7/14;H03L7/199 主分类号 H03L7/18
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