| 摘要 |
PROBLEM TO BE SOLVED: To provide a desired variable delay amount by stabilizing the operation of the variable delay circuit composed of unit variable delay circuits for plural stages. SOLUTION: Input signals ina and inab are delayed just by time based on a control signal cont by a unit variable delay circuit 221 , and output signals S221 a and S221 b are outputted. The amplitude of output signals S221 a and S221 b is smaller than that of input signals ina and inb and through the stages of unit variable delay circuits, the amplitude of output signals is decreased. The maximum value of output signals S22k a and S22k b from a unit variable delay circuit 22k is higher than the minimum value in the high level area by 15%. The output signals S22k a and S22k b are shaped into much higher level by a buffer 23 and outputted as output signals S23a and S23b. Based on the control signal cont, the output signals S23a and S23b are transmitted while being successively delayed by unit variable delay circuits 22k+1 -22m . |
