| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce failures of transferring a signal which is caused by delay of a signal propagation time between circuits by distributing a 1st wiring from a clock output circuit, serially connecting it to plural 2nd circuits, distributing a 2nd wiring from a 1st circuit and connecting it in series to plural memory modules. SOLUTION: A memory controller 32 outputs data for write and a clock signal from output circuits 12 and 11 respectively. An outputted clock signal transmits through a clock wiring, transmits to each connector in order of connectors 34A, 34C,...34E, 34F,...34D and 34B and returns to the controller 32 again. Because write data is also connected to the connectors in the order that is the same as the clock wiring order, it transmits to each connector in the same order. An SDRAM of a memory module that is connected to an optional connector 34 synchronizes with a received clock signal in an input circuit and fetches data from the input circuit 2.</p> |
